To facilitate the testing of an integrated circuit at different back-bias voltages, a popular technique is to form a conductive back-bias pad that is coupled to a substrate region, such as a well or a portion of the substrate itself. Today, many manufacturers set the thresholds of the transistors that compose their integrated circuits by biasing the bulk regions of the transistors with a substrate- or well-bias voltage. (The bulk regions are the substrate or well regions in which the transistor channels are formed.) For clarity, such a bias voltage is hereinafter referred to as a substrate-bias voltage, it being understood that this term also encompasses bias voltages applied to wells or other regions of an integrated circuit. When a substrate-bias voltage other than a supply voltage is to be used, it is often desirable to test a circuit with different values of the substrate-bias voltage to determine an optimum value. To allow such testing, the conductive substrate-bias pad is formed in an upper layer of the circuit and is coupled to a substrate region as described above. During testing, a test probe contacts the pad and supplies the different values of the substrate-bias voltage. But during normal operation of the circuit, the substrate-bias voltage is typically generated by an onboard charge pump. Therefore, because it is needed only during the testing of the circuit, the bias pad is typically not bonded out to a pin of the circuit package, and is thus typically inaccessible to the customer.
Because the bias pad is connected to the substrate region during processing of the integrated circuit, the pad and any conductive regions that are in electrical contact with the pad may deposit or etch at significantly different rates than conductive regions that are in the same layers, respectively, as the other conductive regions but that are insulated from the pad. During processing, the substrate, i.e., the "back" of the wafer, is typically biased at a first voltage potential, and the layers formed on the substrate, ie., the "front" of the wafer, are either biased or allowed to float to a different voltage potential to allow the processing of these layers. Furthermore, the etch and deposition rates of the materials that compose the layers often depend on the voltage potential of the wafer front. Because the bias pad is coupled to the substrate, it is at a different potential than the rest of the wafer front. Therefore, the bias pad and the conductive regions in contact with the pad may etch and deposit at rates that are different than expected.
Unfortunately, the different etch and deposition rates may cause defects in the integrated circuit. For example, a passivation layer is often formed over the bias pad and other portions of the wafer, and then is etched to expose the bias pad and other pads. The amount of etching is based on the anticipated thicknesses of the passivation layer and the respective pads. But if the bias pad is thinner than the other pads because its different potential caused it to be under-deposited, then the etch may not go all the way through the passivation layer to the bias pad, which thus remains unexposed. Or, if the bias pad is thicker than the other pads because its different potential caused it to be over-deposited, then the etch may damage the bias pad. Unfortunately, an unexposed or damaged bias pad often cannot be probed.